A FPGA Based Architecture of Rank Order Filtering For Image Processing Applications

An Integration Circuit is an extremely complex task. It is continually stress the fact that the field is inherently multidisciplinary in nature. By keeping Very large scale integration as a reference we consider the field programmable gate array (FPGA) technology has become an advanced target for the implementation of real time algorithms suited to video image processing applications. The unique architecture of the FPGA has allowed the technology to be used in many applications encompassing all aspects of video image processing. The algorithm like non-linear two dimensional rank order filtering represent a basic set of image operations for a number of applications. An implementation of nonlinear rank order median image filtering using a FPGA Xilinx, vertex-4 is presented. The system is connected to a Universal serial bus port of a personal computer, which in that way form a powerful computing system. The FPGA-based system is accessed through a Mat lab graphical user interface, which handles the communication setup. A Hardware description language is used for coding purpose. The results obtained from Mat lab simulations and the described FPGA-based implementation is presented. Index Termimage, processing, filtering, VHDL/Verilog, Matlab, FPGA.